Congratulations ! Three papers are accepted by ISSCC 2009 1. "A 43.7mW 96GHz PLL in 65nm CMOS" 2. "A 128.24-to-137.00GHz Injection-Locked Frequency Divider in 65nm CMOS" 3. "A Leakage-Suppression Technique for Phase-Locked Systems in 65nm CMOS"
Congratulations ! Five papers are accepted by A-SSCC 2008 1. "A 57.1-59GHz CMOS Fractional-N Frequency Synthesizer Using Quantization Noise Shifting Technique" 2. "A 4-bit 10GSample/sec Flash ADC with Merged Interpolation and Reference Voltage" 3. "A Sub-1V Low-Dropout Regulator with an On-chip Voltage Reference" 4. "A 15-20GHz Delay-Locked Loop in 90nm CMOS Technology" 5. "20Gb/s 1/4-rate and 40Gb/s 1/8-rate Burst-Mode CDR Circuits in 0.13um CMOS"
Congratulations ! Four papers are accepted by Symposium on VLSI Circuits 2008 1. "A Dual-band 61.4~63GHz/75.5~77.5GHz CMOS Receiver in a 90nm Technology" 2. "A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers" 3. "93.5~109.4GHz CMOS Injection-locked Frequency Divider with 15.3% locking range" 4. "A 40Gb/s Low-Power Analog Equalizer in 0.13um CMOS Technology"
Congratulations ! Three papers are accepted by RFIC 2008 1. "Frequency Dividers with Enhanced Locking Range" 2. "A Digitally Calibrated 64.3-66.2GHz Phase-Locked Loop" 3. "A 40GHz Fractional-N Frequency Synthesizer in 0.13£gm CMOS"
